1. Field of the Invention
This invention relates generally to integrated simiconductor structures, and more particularly, to integrated semiconductor structures which incorporate both linear and I.sup.2 L type bipolar devices and fabrication methods therefor.
2. Description of the Prior Art
In the past, various integrated semiconductor structures have been designed which have incorporated generally one type of device such as a linear type device or a digital type device such as, for example, I.sup.2 L type devices.
However, as the technology made significant advances, integrated circuit designers began to realize that there were great advantages to incorporating more than one type of device and circuit into the same integrated structure. Thus, the technology advanced to the point where integrated circuit designers began to incorporate both linear and I.sup.2 L type structures and circuits into a single monolithic integrated semiconductor structure for the obvious advantages of having both linear and digital type circuits in one monolithic integrated semiconductor structure or chip. The particular advantage of incorporating I.sup.2 L and linear type devices and circuits in a single monolithic integrated structure is that I.sup.2 L type devices are generally considered to be compatible to linear type devices because they both can use the same type of semiconductor processing to form the various regions which make up both the linear and I.sup.2 L type structures.
Certain very significant disadvantages became readily apparent in fabricating integrated semiconductor structures which utilized both linear and I.sup.2 L type devices in the same monolithic integrated semiconductor structure. One of these major disadvantages was the lack of compatibility in the resistivity (of the epitaxial layer) needed for the linear type device as compared to the resistivity required (for the epitaxial layer) used in the I.sup.2 L type device. Monolithic integrated structures that used either the linear type resistivity for the epitaxial region for both the linear and the I.sup.2 L type devices or the I.sup.2 L type resistivity for the epitaxial region for both the linear and the I.sup.2 L type devices usually resulted in low efficiency devices being made for either the linear portion (of the monolithic integrated semiconductor structure) or the I.sup.2 L portion.
The use of thick epitaxial layers for these types of monolithic integrated semiconductor structures could not be tolerated for the I.sup.2 L portion of the integrated structure whereas the use of thin epitaxial regions, while providing advantages for the I.sup.2 L portion of the structure, caused a reduction in the performance of the linear portion of the integrated structure. Thus, a great dilemma existed as to how to incorporate both linear and I.sup.2 L type bipolar devices in a single integrated structure and make them both operate at optimum efficiencies.
Accordingly, a need existed to provide a monolithic integrated semiconductor structure and fabrication process therefor that could utilize both I.sup.2 L type devices and linear type devices wherein both the linear and I.sup.2 L devices could operate with maximum efficiency.